The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device, which has a pattern forming step.
Conventionally, in manufacturing semiconductor devices, the following pattern forming process is used in many cases. First, a resist is applied on a thin film such as a silicon oxide film formed on a silicon substrate to form a resist film. Next, the resist film is pattern-exposed and developed so that a resist pattern is formed. Furthermore, using the resist pattern as an etching mask, a thin film such as a silicon oxide film or a surface of the silicon substrate is etched. Thereafter, the resist film is removed by ashing.
By the way, in recent years, as the degree of integration of a device increases, a margin of dimension or the like tends to become narrow in the above pattern forming process. For this reason, in order to form a finer pattern with a high precision, a technique such as utilization of exposure light having a shorter wavelength, utilization of an antireflection film for reducing influence of reflected light from a substrate, and decreasing the thickness of a resist film has been utilized.
However, in order to achieve a pattern size of less than 0.2 μm, the thickness of a resist film must be thinned down to 0.2 μm or so. When the resist film is thin, of course, the thickness of the resist pattern is also made thin. Such a thin resist pattern is insufficient as a mask for etching, particularly, reactive ion etching (hereinafter, called RIE) for forming contact holes having-a depth of 1 μm or more. Accordingly, in the above pattern forming process, it has been difficult to implement such a pattern forming with a high precision.
As an effective method for solving such a problem, the following method is known. First, a polysilicon film where a high etching selectivity can be achieved is formed on a silicon oxide film. Next, a resist pattern is formed on the polysilicon film. Then, using the resist pattern as a mask, the polysilicon film is etched so that a polysilicon pattern is formed. Furthermore, using the polysilicon pattern as a mask, the silicon oxide film is etched. In the above manner, a contact hole is formed in the silicon oxide film.
In the above-mentioned method, the resist pattern is utilized for patterning the polysilicon film, and the polysilicon pattern is utilized as a mask for patterning the silicon oxide film. Therefore, according to this method, it is possible to form a contact hole with a relatively high precision.
In this method, however, the polysilicon pattern which has been used as the mask is removed by etching. For this reason, according to the above method, there occurs a problem that a portion of the silicon substrate exposed at a bottom of the contact hole is also etched.
In the conventional pattern forming process, there are also problems other than the above.
For example, when an organic SOG (Spin On Glass) film is used as an inter-layer insulating film, CF4/O2 down flow ashing or O2 plasma ashing is utilized in order to remove the resist pattern which has been used for the pattern forming. When the resist pattern is removed by such a method, a reaction between organic components contained in the organic SOG film and oxygen radical or the like occurs. As a result, there occurs a problem that the composition in the organic SOG film varies and the dielectric constant ∈ of the organic SOG film becomes larger than that of a design value.
Also, as a structure where parasitic capacity between an upper wiring and a lower wiring can be reduced, an air wiring structure having no inter-layer insulating film has been proposed. The air wiring structure is formed by a damascene process using a carbon film as a dummy layer in which wiring material is embedded. That is, first, a lower wiring is embedded in an insulating layer on a semiconductor substrate. Next, a carbon film is formed on the lower wiring and the insulating film by sputtering method. Thereafter, an SiO2 film is formed on the carbon film, and a resist pattern is formed on the SiO2 film. Furthermore, using the resist pattern as a mask, a wiring groove is formed in the carbon film by RIE method. Next, a thin film made of wiring material is formed such that it is embedded in the groove for wiring. A portion of the thin film positioned outside the wiring groove is removed using a chemical-mechanical polishing (CMP) method, so that the upper wiring is formed. Then, the carbon film is removed by O2 ashing step. Thus, the air wiring structure is formed.
In the above-mentioned method, oxygen radical is supplied to the carbon film through the SiO2 film to cause reaction between the oxygen radical and the carbon, so that the carbon film is removed. Therefore, the rate at which the carbon film is removed is affected largely by the SiO2 film. That is, in the conventional method, there is a problem that it takes much time to form the air wiring structure.